It is widely accepted that although bulk silicon MOS transistors can be scaled below the 45 nm technology node, the historical 17% performance enhancement per year might not be guaranteed. Besides that, the escalated complexity of integrated circuits has also raised new challenges for on-chip power management. In order to sustain the phenomenal progress in information processing and transmission, innovative device structures and new materials have to be considered. In this talk, we will first illustrate the importance of high mobility channel in nanoscale transistors and justify the choice of germanium. In addition, we will review various germanium MOS device fabrication technology on nanoscale gate stack, shallow source/drain junction, and low thermal budget process integration. Moreover, we will benchmark these advanced processes against the state-of-the-art silicon technology.

  Prof. Chui has conducted research in the broad areas of germanium-based solid-state devices ranging from device physics, fabrication nanotechnology, as well as physical and electrical characterizations. A major part of his work was on the seminal integration of high-permittivity nanoscale gate dielectrics into germanium channel MOS transistors with significant carrier mobility enhancement demonstrated. Besides, he had maintained a strong interest in Group IV optoelectronic devices and specialized in high-speed and low-noise photodetectors. His current research interests include ultra-low power and very high performance nanoelectronics for digital and RF circuit applications. He has authored or co-authored over 70 technical papers (including 20 invited papers) and 4 book chapters. He has also received two best paper awards and holds one issued and few pending US patents. Very recently, he was honored with the 2007 Okawa Foundation Award.