| Now that high-performance microprocessors have sprinted past the gigahertz mark with millions of transistors switching more than billion times per second, accounting for clock skew, signal delay, peak-power dissipation (among other phenomena), has become increasingly difficult on conventional synchronous designs, where all transistors march to the same beat. This reality makes the asynchronous alternative, Professor Yun's focus, a critical area of research. ..Yun is a developer of formal and automated techniques for managing multiple independently synchronized domains on a processor under a methodology in which timing and communication can be explicitly specified, synthesized, analyzed, and verified. Research areas include: mixed-timing interface design methodologies and components; specification formalism for mixed-timing interfaces; performance-driven synthesis and technology mapping techniques for mixed-timing circuits; hierarchical timing verification techniques that check the validity of assumptions used for synthesis and technology mapping; and techniques to estimate and analyze system performance. The work takes on new urgency given the shift to system-on-chip schemes.
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