High Performance and Energy Efficient SoC Design Challenges and Opportunities for the Sub-10nm Technology Era: From AI to IoT Platforms


Jacobs Hall, Room 2512, Jacobs School of Engineering, 9500 Gilman Dr, La Jolla, San Diego, California 92093

Sponsored By:
Professor Patrick Mercier

Ram K. Krishnamurthy
Senior Research Director and Senior Principal Engineer
Intel Labs
Ram K. Krishnamurthy


This lecture presents some of the prominent barriers to designing high performance and energy-efficient microprocessors and digital systems-on-chip in the sub-10nm technology regime and outlines new paradigm shifts necessary in next-generation tera-scale multi-core microprocessors and systems-on-chip. Emerging trends in SoC design for Artificial Intelligence, Machine Learning, and IoT platforms will be discussed, and key challenges in sub-10nm design are outlined, including (i) device and on-chip interconnect technology scaling projections, (ii) performance, leakage and voltage scalability, (iii) special-purpose hardware accelerators and reconfigurable co-processors for compute-intensive signal processing algorithms, (iv) fine-grain power management with integrated voltage regulators, and (v) resilient circuit design to enable robust variation-tolerant operation. Energy-efficient arithmetic and logic circuit techniques, static/dynamic supply scaling, on-die interconnect fabric circuits, ultra-low-voltage and near-threshold logic and memory circuit techniques, and multi-supply/multi-clock domain design for switching and leakage energy reduction are described. Special purpose hardware accelerators and data-path building blocks for enabling high GOPS/Watt on specialized DSP tasks such as machine learning, encryption, graphics and video/media processing are presented. Power efficient optimization of microprocessors to span a wide operating range across high performance servers to ultra-mobile SoCs, dynamic on-the fly reconfigurability and adaptation, and circuit techniques for active/standby-mode leakage reduction with robust low-voltage operability are reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed. Finally, emerging industry trends in neuromorphic computing will be outlined.

Speaker Bio:
Ram K. Krishnamurthy is a Senior Research Director and Senior Principal Engineer at Intel Labs, Hillsboro, Oregon. He heads the high performance and low voltage circuits research group. In this role, he leads research in high performance, energy efficient, and low voltage circuits for microprocessors and SoCs, and has made contributions to the circuit design of various generations of Intel products, including Intel® Itanium®, Pentium4®, Core®, Atom® and Xeon® line of microprocessors and SoCs. He has been at Intel Corporation since 1997.Krishnamurthy has filed over 160 patents (115 issued), and has published 150 papers and 3 book chapters on high performance energy efficient circuits. He serves as chair of the Semiconductor Research Corporation (SRC) technical advisory board for circuits, has been a guest editor of IEEE Journal of Solid-State Circuits, associate editor of IEEE transactions on VLSI systems, and on the technical program committees of ISSCC, CICC, and SOCC conferences. He served as Technical Program Chair/General Chair for the IEEE International Systems-on-Chip Conference and presently serves on the conference’s steering committee. Krishnamurthy serves as an adjunct faculty of the Electrical and Computer Engineering department at Oregon State University, where he taught advanced VLSI design. He is a board member of the industry advisory board for State University of New York. Krishnamurthy has received the IEEE International Solid State Circuits Conference distinguished technical paper award, IEEE European Solid State Circuits Conference best paper award, outstanding industry mentor award from SRC, Intel awards for most patents filed and most patents issued, Alumni recognition award from Carnegie Mellon University, distinguished alumni award from State University of New York, MIT Technology Review’s TR35 innovator award, and recognized as a top ISSCC paper contributor. He has received two Intel Achievement Awards for pioneering the first sparse-tree ALU technology and the first AES security accelerator on Intel products. He is a Fellow of the IEEE and distinguished lecturer of IEEE solid-state circuits society. Krishnamurthy received his BE in electrical engineering from National Institute of Technology in India (1993), MS in electrical and computer engineering from State University of New York (1994), and PhD in electrical and computer engineering from Carnegie Mellon University (1997).

Bethany Carson
Phone: 858-822-6347